Random defects occurring during the manufacturing of an integrated circuit with embedded memory blocks can render certain non-redundant elements of an integrated circuit memory device, such as a memory column, defective. For example, particle contamination during the manufacturing process may cause broken or shorted out columns and bit defects.
Redundant elements in an integrated circuit memory device, such as redundant columns, are used to compensate for these random defects. Initial testing of an integrated circuit memory occurs after the manufacturing process. During initial testing of an integrated circuit memory device, defective elements are replaced by non-defective elements referred to as redundant elements. Thus, redundant columns may be used in a scheme to replace defective non-redundant columns, discovered during initial testing of the integrated circuit memory device. The use of redundant elements is important in increasing the overall yield of an integrated circuit memory device.
Repair algorithms allocate these redundant elements to substitute for known defective elements. A more complicated repair algorithm usually has a higher success rate in repairing a given memory but also takes up more space on a chip.
An example of such a complete repair algorithm starts the repair analysis with the full set of redundant elements associated with that memory. The repair analysis also runs various sequences of the potential repair algorithms in parallel.
However, a disadvantage to logic that runs the various repair algorithms in parallel is the physical space required on the chip for each engine running one of the algorithms. Each repair algorithm run in parallel uses a separate logic engine. Each logic engine takes up space on the chip that could be used for extra memory capacity or processing power on that chip.
Another disadvantage is when starting a repair of a memory with full set of redundant components, the resultant repair signature may not be the most efficient repair with the redundant components available. When later defects occur in other memory bank that share the same redundant components or defects occur in that memory during field operations, then the redundant components may not be available to fix the memory faults.
FIG. 1 illustrates a block diagram of an exemplary memory having several defects that is repairable using two or more combinations of the available redundant components. The exemplary bank memory contains four defective memory cell addresses. The exemplary memory has four redundant components in the full set of redundant components, 2 Rows and 2 Columns. The exemplary bank memory has 6 possible repair sequences with the full set of redundant components. The 6 possible repair sequences can be applied to the memory in a row, row, column, column, (RRCC) sequence, a row, row, column, column, row, (RCCR) sequence, a row, column, row, column, (RCRC) sequence, a column, column, row, row, (CCRR) sequence, a column, row, column, row, (CRCR) sequence, and a column, row, row, column (CRRC) sequence.
For example, in the RRCC sequence, the first defective memory cell address is repaired by allocating a redundant row to repair the defect. The second defective memory cell address is also repaired by allocating a redundant row to repair the defect. The third defective memory cell address is repaired by allocating a redundant column to repair the defect. The fourth defective memory cell address is also repaired by allocating a redundant column to repair the defect.
Multiple repair sequences can repair the memory such as CCRR and CRRC. FIG. 1 illustrates graphically how the two repair sequences would repair the memory. However, the CRRC is more efficient because this repair sequence only needs to allocate one redundant row and two redundant columns to completely repair the memory. Thus, one redundant row remains not allocated. Nonetheless, when all the repair sequences are run in parallel, then no guarantee exists that the eventual repair signature will be based upon the CRRC repair sequence.